1. Field of The Invention
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device comprising a semiconductor chip and bump electrodes, in which the semiconductor chip is coupled to an electronic component including a semiconductor chip via the bump electrode so that the semiconductor chip is opposed to the electronic component, and the bump electrode is encapsulated with an underfill composed of an insulating resin.
2. Related Art
In recent years, under circumstances of an enhanced integration and an enhanced processing rate for a semiconductor device, a chip-on-chip (COC) coupling technology that involves coupling different chips through an bump electrode by the shortest paths is expected in terms of achieving a practical realization thereof, which can provide creating a high-speed system composed of different LSI devices with lower cost that requires shorter time for the development.
Further, in chips employed for creating the COC coupling, an increased number of pins for providing a coupling to other devices are required, under circumstances of an increasing demand for an enhanced miniaturization and sophistication of semiconductor devices, and therefore reductions in an interval between chips and a dimensional shrinkage of bumps are achieved. This simultaneously causes reducing an interval between upper and lower chips and reducing a geometry of a spacing between bumps, and therefore it is difficult to inject an insulating underfill resin between the bump and the chip. Further problems may be caused in such configuration that air bubbles are easily generated in the resin (i.e., generating voids), and the generated air bubbles are difficult to be eliminated.
Further problem may be caused when an insulating film such as polyimide (PI) film is formed in an area except the bumps-formed region, in order to provide a protection to surface of the chip from the outside. The presence of such insulating film may provide a reduced gap between the upper chip and the lower chip and/or may provide a deteriorated flowability of the underfill resin that is in contact with the insulating film, blocking an approach of the underfill resin particularly in a stepped portion of the insulating film, and therefore there is a fear that peripheral portions of the bump are not suitably filled with the underfill resin.
Japanese Patent Laid-Open No. 2003-324,182 discloses a technology that aims for preventing a generation of voids in the underfill resin during an injection of the resin for the COC structure, in which the underfill resin is supplied between the upper chip and the lower chip that are mutually coupled. In general, when the interval between the upper and the lower chips is increased, a positional deviation in the distribution of the entering speed of the underfill resin is ordinarily increased and in particular, a tendency of providing lower flow rate in a region closer to the center of the chip and higher flow rate in a region closer to the outside of the chip is presented. This tendency causes the change of flow of the underfill resin entering in the outer region, so that the flow is detoured to the central region, thereby encapsulating air within the resin to create voids therein. On the contrary, according to the above-described conventional technology, the flow rates of the resin in respective regions are adjusted to be harmonized, thereby preventing the generation of voids.
In the meantime, when the interval between the upper and the lower chips is further reduced for achieving higher miniaturization of the semiconductor device, the flow rate of the resin around the bumps-formed region may be particularly decreased during the supply of the underfill resin, resulting in a generation of voids around the bumps-formed region due to bubbles mixed therein. Further, it is confirmed by the present inventors that a cycle of an expansion and a shrinkage of voids that have been generated around the bumps-formed region are repeated during the temperature cycle test for evaluating a reliability of devices, promoting a stress exerted on the bumps-formed region, such that there is a fear that both of semiconductor chips joined to certain portions of the bumps-formed region are eliminated therefrom.
Concerning the above-described fear, although the technology described in Japanese Patent Laid-Open No. 2003-324,182 addresses a certain solution for avoiding the encapsulation of voids within the device-forming region of the COC structure, no solution for voids possibly generated due to bubbles being mixed around the bumps-formed region is presented.